In a high-capacity recording device such as SSD (Solid State Disk) and HDD (Hard Disk Drive), it is general that parallel data read from a recording region is converted into serial data before being transmitted. Accordingly, the high-capacity recording device has a parallel-serial converter circuit.
As a measure for improving data transfer speed, a plurality of types of parallel data may be simultaneously converted into serial data to transmit these serial data in synchronization with each other. In this case, a plurality of parallel-serial converters are provided in the parallel-serial converter circuit. In such a parallel-serial converter circuit, it is general to start parallel-serial conversion after supplying a reset signal to each parallel-serial converter to reset each parallel-serial converter, to synchronize the parallel-serial converters and eliminate a timing gap therebetween.
However, since the reset signal is used also in the components other than the parallel-serial converter circuit, the reset signal path to be routed often becomes long. Accordingly, the load capacity of the reset signal becomes large, which lengthens the rise time of the reset signal. Further, the rise time of the reset signal differs depending on each parallel-serial converter in the same chip, due to the influence of manufacturing process, power-supply voltage, junction temperature, etc. It is difficult to predict this difference to make a design for restraining the timing gap in the reset signal.
Each parallel-serial converter performs parallel-serial conversion based on a clock signal obtained by dividing the frequency of a reference high-speed clock signal by a frequency divider. It is not easy to design the timing considering a time gap after the rising edge of the reset signal is detected before the frequency divider starts its operation. In particular, the design is made more difficult as the speed of the parallel-serial conversion increases.
As stated above, when a plurality of parallel-serial converters are provided in the parallel-serial converter circuit, it is difficult to synchronize the parallel-serial converters for the above reasons even if each parallel-serial converter is a circuit capable of operating at high speed, which leads to a problem that data transfer speed cannot be increased so much.